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Zarlink Semiconductor
Zarlink Semiconductor

PX6420 Datasheet Preview

PX6420 Datasheet

Multi-Rate TIA/LA Optical Receiver

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PX6420 pdf
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Features
• Integrated transimpedance and limiting
amplifier for serial optical receiver
applications
• Receiver sensitivity 20 µApp for 10-12 BER at
10 Gb/s
• Receive signal strength indicator (RSSI) for
digital diagnostics and active alignment
• Loss of signal indicator (LOS)
• Optional squelch circuit disables output at low
input levels
• Back-terminated 50-ohm CML output
providing 250 mVpp differential amplitude
• No external passives required for photodiode
bias network
• Single +3.3 V supply dissipating 115 mW
Applications
• 850 nm and 1310 nm receive optical sub-
assemblies (ROSA)
• XFP, X2, XPAC, XENPAC optical modules
• 10GbE, 10GFC, 8GFC, 4GFC, OC-192 VSR
• Proprietary back plane optics
PX6420
Multi-Rate TIA/LA Optical Receiver
Product Brief
September 2004
Description
The growing use of the Internet has created
increasingly higher demand for multi-Gb/s I/O
performance. The demand and availability of 10
Gb/s+ WAN bandwidth fuels the growth of native
10 Gb/s infrastructures within MAN and enterprise
datacenters.
The Primarion® PX6420 10 Gb/s receiver is a
single channel TIA/LA optical receiver designed for
various 10 Gb/s PMD applications. It consists of a
transimpedance amplifier and an AC-coupled
differential limiting amplifier.
The transimpedance amplifier achieves a nominal
bandwidth of 8 GHz over a wide range of
photodiode input capacitance. A photodiode bias
current monitor allows for a simple alignment
procedure.
The transimpedance amplifier is AC-coupled
internally to a high-gain, high-bandwidth, limiting
amplifier. The limiting amplifier provides a
differential back-terminated CML output that can
be used to drive 10 Gb/s Serdes or other CML
compatible circuits.
Full diagnostics are delivered through loss of
signal, squelch, and received signal strength
indicator circuits.
1
Zarlink Semiconductor Inc.



Zarlink Semiconductor
Zarlink Semiconductor

PX6420 Datasheet Preview

PX6420 Datasheet

Multi-Rate TIA/LA Optical Receiver

No Preview Available !

PX6420 pdf
PX6420
Figure 1: 10 Gb/s differential data output using a PRBS23 optical data input pattern
Product Brief
Figure 2: Diagram shows a typical bonding configuration
for the PX6420 mounted on a TO-46 header.
The figure shows a photodiode attached directly
on the PX6420 IC. Also shown are two
microwave chip capacitors used for VCC
decoupling. Capacitor values of 200 fF are
typical but vary by application environment.
Figure 3: Similar configuration as Figure 2. Sq_En
connected to VCC disables the limiting amplifier
when LOS is asserted.
Chip-Cap
3.3 V
3.3 V
GND
GND
Rate
SReSleScIt
1200
DP DP
DN DN
Chip-Cap
Required
Chip-Cap
3.3 V
3.3 V
GND
Rate
SReSleScIt
GND
1200
DP DP
DN DN
Optional
Chip-Cap
2
Zarlink Semiconductor Inc.


Part Number PX6420
Description Multi-Rate TIA/LA Optical Receiver
Maker Zarlink Semiconductor
Total Page 3 Pages
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