Datasheet Details
| Part number | S5933QE |
|---|---|
| Manufacturer | AMCC |
| File Size | 125.58 KB |
| Description | PCI Interface Device Summary |
| Download | S5933QE Download (PDF) |
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| Part number | S5933QE |
|---|---|
| Manufacturer | AMCC |
| File Size | 125.58 KB |
| Description | PCI Interface Device Summary |
| Download | S5933QE Download (PDF) |
|
|
|
: When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasserts FRAME# on the next clock to indicate the last data phase is in progress.
If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME# has already been deasserted.
Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent this event from occurring.
www.DataSheet4U.com PCI Interface Device Summary S5933QE Revision 4 January 6, 1999 Factory Device Update The following are all known device and document errors for the AMCC S5933 PCI Matchmaker revision QE and the 1998 device data book.
The workarounds described below are factory suggestions and are not to imply the only or all possible solutions.
Contact your local Field Application Engineer for new workaround developements.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
| ETC | S5933QE | Controller Device Summary | ETC |
| Part Number | Description |
|---|---|
| S5933 | 32-Bit PCI MatchMaker |
| S5935 | 32-Bit Pci Bus Master/target |