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AMI

DC31 Datasheet Preview

DC31 Datasheet

CMOS Gate Array

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'&[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
DC3x is a family of three-to-eight line decoder/demultiplexers with active low enable.
Logic Symbol
Truth Table
DC3x
E
Q0
Q1
S2 Q2
S1 Q3
S0 Q4
Q5
Q6
Q7
EN S2 S1 S0 Q0N Q1N Q2N Q3N Q4N Q5N Q6N Q7N
HXXXHHHHHHHH
L L L L LHHHHHHH
L L LHHLHHHHHH
L LHLHHLHHHHH
L LHHHHHLHHHH
LHL LHHHHLHHH
L H L HHHHHH L HH
L HH L HHHHHH L H
L HHHHHHHHHH L
HDL Syntax
Verilog .................... DC3x inst_name (Q0N, Q1N, Q2N, Q3N, Q4N, Q5N, Q6N, Q7N, EN, S0, S1, S2);
VHDL...................... inst_name DC3x port map (Q0N, Q1N, Q2N, Q3N, Q4N, Q5N, Q6N, Q7N, EN, S0, S1, S2);
Pin Loading
Pin Name
S0
S1
S2
EN
Equivalent Loads
DC31
DC32
5.8 5.7
5.4 5.7
5.3 5.3
1.0 1.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
DC31
20.0
TBD
39.8
DC32
29.0
TBD
61.2
a. See page 2-15 for power equation.
3-47




AMI

DC31 Datasheet Preview

DC31 Datasheet

CMOS Gate Array

No Preview Available !

'&[
$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
DC31
From: Sx
To: QN
tPLH
tPHL
From: EN
To: QN
tPLH
tPHL
Number of Equivalent Loads
0.33
0.50
0.51
0.70
1
2
0.36
0.59
0.55
0.77
4
DC32
From: Sx
To: QN
tPLH
tPHL
0.23
0.43
0.33
0.60
From: EN
To: QN
tPLH
tPHL
0.80
1.09
0.90
1.22
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
Logic Schematic
S0
S1
S2
EN
4
0.42
0.76
0.63
0.94
8
0.44
0.78
1.02
1.38
®
5 7 (max)
0.44 0.49
0.84 1.00
0.67 0.73
1.03 1.20
13 17 (max)
0.57 0.68
0.97 1.12
1.15 1.25
1.58 1.74
Q0N
Q1N
Q2N
Q3N
Q4N
Q5N
Q6N
Q7N
3-48


Part Number DC31
Description CMOS Gate Array
Maker AMI
Total Page 2 Pages
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