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DF401 - CMOS Gate Array

General Description

DF40x is a family of static, master-slave, multiplexed scan D flip-flops.

SET is asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

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Datasheet Details

Part number DF401
Manufacturer AMI
File Size 46.03 KB
Description CMOS Gate Array
Datasheet download datasheet DF401 Datasheet

Full PDF Text Transcription for DF401 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DF401. For precise diagrams, and layout, please refer to the original PDF.

')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF40x is a family of static, master-slave, multiplexed scan D flip-flops. SET is asynchronous and active low. Outputs...

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iplexed scan D flip-flops. SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF40x DS C SD SE Q Q Truth Table C D SD SE SN Q QN ↑HX LHHL ↑LXLHLH ↑ XHHHH L ↑X LHHLH XXXXLHL L X X X H NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF40x inst_name (Q, QN, C, D, SD, SE, SN); VHDL...................... inst_name: DF40x port map (Q, QN, C, D, SD, SE, SN); Pin Loading Pin Name C D SD SE SN DF401 1.0 1.0 1.0 2.1 2.1 Equivalent Loads DF402 DF404 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.2 2.1 3.1 DF406 1.0 1.0 1.0 2.2 3.

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