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DF412 - CMOS Gate Array

Download the DF412 datasheet PDF. This datasheet also covers the DF411 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

DF41x is a family of static, master-slave, multiplexed scan D flip-flops.

RESET is asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DF411-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DF412
Manufacturer AMI
File Size 46.34 KB
Description CMOS Gate Array
Datasheet download datasheet DF412 Datasheet

Full PDF Text Transcription for DF412 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DF412. For precise diagrams, and layout, please refer to the original PDF.

')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF41x is a family of static, master-slave, multiplexed scan D flip-flops. RESET is asynchronous and active low. Outpu...

View more extracted text
iplexed scan D flip-flops. RESET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF41x D C SD SE R Q Q Truth Table C D RN SD SE Q QN ↑HHX LHL ↑LHXL LH ↑ XHHHH L ↑XHLHLH XXLXXLH L X H X X NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF41x inst_name (Q, QN, C, D, RN, SD, SE); VHDL...................... inst_name: DF41x port map (Q, QN, C, D, RN, SD, SE); Pin Loading Pin Name C D RN SD SE DF411 1.0 1.0 1.0 1.0 2.1 Equivalent Loads DF412 DF414 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.2 DF416 1.0 1.0 1.0 1.0 2.

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