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MG29C01 Datasheet Preview

MG29C01 Datasheet

4-Bit microprocessor

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MG29C01 pdf
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Features
• A high-performance, low-power CMOS megacell
featuring functional compatibility with the industry
standard 2901
• 4-Bit cascadable bit-slice
• Eight function ALU including addition, two subtraction
and five logic operations on two operands
• Microprogrammable with three groups of three bits each
for ALU function, destination control and source
operand
• Two address architecture provides independent access
to two working registers
• Five source ports for data selection
• Four status flags including carry, zero, overflow and sign
• Equivalent gates:
Standard Cell - 810; Gate Array - 1000
LOGIC SYMBOL
MG29C01
I(8:0)
Q0I
Q3I
RAM0I
RAM3I
CIN
CLK
Q0O
Q3O
F0
F3
GN
PN
COUT
OVR
RAM0O
RAM3O
OE0N
OE3N
Description
MG29C01 is a high-performance 4-bit cascadable
microprocessor.
The MG29C01 offers the designer a simple and methodi-
cal approach to designing bit-slice microprocessors, high-
speed ALUs and boolean machines.
The MG29C01 consists of a fast ALU, a 16-word by 4-bit
two port RAM and the required decoding, multiplexing
and shifting circuits. The microinstruction word consists of
nine bits divided into three groups. Bits 0-2 select the ALU
source operads. Bits 3-5 select the ALU function and bits
6-8 select the destination register.
The ALU allows for several arithmetic functions which
include: unsigned addition and subtraction, two’s comple-
ment and one’s complement addition and subtraction,
and decrementing. The ALU also produces the status
bits: overflow, carry-out, F0. Boolean functions offered
include: AND, OR, XOR, XNOR, INVERT, PASS, ZERO,
and MASK.
The MG29C01 also includes a 16-word by 4-bit register,
a 4-bit Q register, and various sources for the ALU.
D(3:0)
A(3:0)
B(3:0)
Y(3:0)
5-5



AMI
AMI

MG29C01 Datasheet Preview

MG29C01 Datasheet

4-Bit microprocessor

No Preview Available !

MG29C01 pdf
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%LW 0LFURSURFHVVRU
®
'LJLWDO 6RIW 0HJDFHOOV
Pin Description
SIGNAL
I(8:0)
CIN
CLK
D(3:0)
A(3:0)
B(3:0)
Q0O, Q3O
Q0I, Q3I
F0
F3
GN, PN
COUT
OVR
OE0N
OE3N
RAM0O,
RAM3O
RAM0I,
RAM3I
Y(3:0)
TYPE
Input
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
Output
Output
SIGNAL DESCRIPTIONS
The nine instruction lines.
Carry in to the ALU.
The clock input.
Data inputs. These data may be selected as one of the ALU sources. D(0) is the LSB.
The address inputs to the register stack, used to select which register’s contents are
available through the A port. A(0) is the LSB.
The address inputs to the register stack used to select which registers contents are
available through the B port. B(0) is the LSB.
The input and output shift lines for the LSB and MSB of the Q register, allow for shift up
and shift down operations. Q3 is the MSB. Q0O is valid when OE0N is low and Q3O is
valid when OE3N is low.
Becomes active when all four ALU outputs are low.
The most significant ALU output bit.
The generate and propagate outputs of the ALU, can be used to for carry look-ahead.
Carry out of the ALU.
Overflow. Indicates the result of an arithmetic two’s complement operation has
overflowed into the sign bit.
A low on this pin indicates Q0O and RAM0O are valid.
A low on this pin indicates Q3O and RAM3O are valid.
The input and output shift lines for the LSB and MSB of the register stack, allow for shift
I/O up and shift down operations. RAM3 is the MSB. RAM0O is valid when OE0N is low and
RAM3O is valid when OE3N is low.
Output Data outputs. These outputs are connected to either ALU or A port of the register stack.
5-6


Part Number MG29C01
Description 4-Bit microprocessor
Maker AMI
Total Page 2 Pages
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