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MG65C02 Datasheet Preview

MG65C02 Datasheet

8-bit microprocessor

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Features
• High-performance, schematic-based megacell
• Functional compatibility with the industry standard 6502
• 8-Bit Microprocessor
• Fully Static Design
• 0-33 MHz Operation
• 64 kbytes Program Address Space
• Enhanced Instruction Set
• Supports Bit Manipulation
• 72 instructions and 212 opcodes
• 15 address modes
• Interrupt Capability
• Equivalent gates:
Standard Cell - 2,950; Gate Array - 3,850
LOGIC SYMBOL
MG65C02
Description
MG65C02 is an 8-bit microprocessor which is compatible
with the industry standard W65C02S. It has been
designed to be compatible with both the original NMOS
6502 and the newer CMOS variations from various
vendors.
The MG65C02 runs all 6502 opcodes as well as the new
Enhanced Instruction set which include the new bit
manipulation opcodes - RMB, SMB, BBR, BBS, and WAI
and STP instructions. The latest functions are also incor-
porated in the MG65C02 such as Bus Enable, Vector-
Pull, and Memory Lock. It accesses 65 kbytes of addres-
sable Memory. It is fully static allowing the external clock
to stop in either state. Operation frequency follows a
range of 0 MHz, for low power or standby modes, to more
than 25 MHz for high speed applications.
RDYI
RESN
IRQN
NMIN
SON
PHI2IN
RDYO
RWN
SYNC
VPN
MLN
PHI1OUTN
PHI2OUT
DBI(7:0)
A(15:0)
DBO(7:0)
DBEN
5-11




AMI

MG65C02 Datasheet Preview

MG65C02 Datasheet

8-bit microprocessor

No Preview Available !

0*&
%LW &RUH 0LFURSURFHVVRU
'LJLWDO 6RIW 0HJDFHOOV
Pin Description
SIGNAL TYPE
A0-A15
O
DBO0-DBO7 O
DBI0-DBI7 I
DBEN
O
RDYI
I
RDYO
O
RESN
I
IRQN
I
NMIN
I
SON
I
RWN
O
SYNC
O
VPN
O
MLN
O
PHI2IN
PHI1OUTN
PHI2OUT
I
O
O
SIGNAL DESCRIPTIONS
Address to memory.
Data bus output. Valid when DBEN is high.
Data bus Input. Should be valid when DBEN is low.
Data Bus Enable.
Ready Input, active low. Stops the internal clock.
Ready Output. The WAI instruction uses this pin to bring RDYI low.
Active low Reset.
Active low Interrupt.
Active low Non-maskable interrupt.
Active low sets the overflow bit in the status word.
Read/Write. Active low for write.
Synchronize. Active during opcode fetch cycle.
Vector Pull, active low. Low during interrupt vector access.
Memory Lock, active low. Low during Read-Modify-Write (RMW) portion of RMW
instructions.
Clock.
Clock. Out of phase with C2IN.
Clock. In phase with PHI2IN. It also goes high with the STP instruction.
®
5-12


Part Number MG65C02
Description 8-bit microprocessor
Maker AMI
Total Page 2 Pages
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