Datasheet Details
| Part number | ODTSXN12 |
|---|---|
| Manufacturer | AMI |
| File Size | 25.34 KB |
| Description | CMOS Gate Array |
| Datasheet | ODTSXN12 ODTSXN04 Datasheet (PDF) |
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Overview: 2'76;1[[ ® $0,+* PLFURQ &026 *DWH $UUD.
This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | ODTSXN12 |
|---|---|
| Manufacturer | AMI |
| File Size | 25.34 KB |
| Description | CMOS Gate Array |
| Datasheet | ODTSXN12 ODTSXN04 Datasheet (PDF) |
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|
ODTSXNxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel open-drains (pulldown) and controlled slew rate outputs.
Logic Symbol Truth Table ODTSXNxx A PADM A PADM LL HZ Z = High Impedance Pad Logic HDL Syntax Verilog ....................
ODTSXNxx inst_name (PADM, A);
| Part Number | Description |
|---|---|
| ODTSXN16 | CMOS Gate Array |
| ODTSXN04 | CMOS Gate Array |
| ODTSXN08 | CMOS Gate Array |
| ODTSXN24 | CMOS Gate Array |
| ODTSXE04 | CMOS Gate Array |
| ODTSXE08 | CMOS Gate Array |
| ODTSXE12 | CMOS Gate Array |
| ODTSXE16 | CMOS Gate Array |
| ODTSXE24 | CMOS Gate Array |
| ODTSXX04 | CMOS Gate Array |