PLU3 array equivalent, cmos gate array.
PLU3 is an active pull-up buffer piece.
Logic Symbol
PLU3
PADM
3/8
$0,+* PLFURQ &026 *DWH $UUD
Truth Table
Pin Loading
N/A N/A
HDL Syntax Verilog .................... PLU3 inst_name (PADM); VHDL...................... inst_name: PLU3 port.
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