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AMI

RASJ810 Datasheet Preview

RASJ810 Datasheet

CMOS Gate Array Memory

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5$6-
® +LJK 6SHHG /RZ3RZHU 6LQJOH 3RUW
$0,+*  PLFURQ &026 *DWH $UUD\ 0HPRULHV
Features
• Self-timed design allows flexibility in clock duty cycle
while maintaining fast cycle time
• 256 x 8 instantiation block
• Always active outputs
• Low standby power when the clock is stopped
• Separate input and output ports with full parallel access
• Altera Flex10 equivalent functionality
• Precharged design for faster operation with lower power
consumption
FIGURE 1: LOGIC SYMBOL
RASJ810
CLK
RASJ810: High Speed Low-Power Single Port
Description
This 256x8 SRAM block is built into AMI's base arrays.
When your application requires static RAM memory, use
these RAMs. The self timed feature of this RAM allows
flexibility in the clock duty cycle while maintaining fast
cycle times. All timing is relative to the risting edge of the
clock input (CLK). When CLK rises, all inputs are latched
and the READ or WRITE operation occurs. The RAM will
stay in the READ mode and not start precharging until the
READ operations is complete, even if CLK falls. The
outputs become valid a short time after the rising edge of
CLK and stay valid unil the next rising edge of CLK. All of
the inputs including CLK can be held stable indefinately
with no loss of memory as long as power is supplied to the
RAM. See figure 2 for a block diagram of the RAM.
To obtain additional data or an EDA model contact your
sales representative or the factory.
WRT
A (7:0)
DI (7:0)
Note: A0 is the LSB.
Q (7:0)
6-1




AMI

RASJ810 Datasheet Preview

RASJ810 Datasheet

CMOS Gate Array Memory

No Preview Available !

5$6-
+LJK 6SHHG /RZ3RZHU 6LQJOH 3RUW
$0,+*  PLFURQ &026 *DWH $UUD\ 0HPRULHV
FIGURE 2: RAM BLOCK DIAGRAM
Timing,
CLK Precharge
and Latch Control
A (7:0)
Row
Decode
Address
Latches
Core
DI (7:0)
WRT
Column
Decode
Write Control
and
Latches
Senseamps
and
Output Latches
Q (7:0)
6-2
®


Part Number RASJ810
Description CMOS Gate Array Memory
Maker AMI
Total Page 6 Pages
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