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SLF024 Datasheet Preview

SLF024 Datasheet

CMOS Gate Array

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6/)[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
SLF02x is a family of static, master-slave, multiplexed scan latch, D flip-flops. When SCE is low it is a D flip-flop with the
output buffered and changes state on the rising edge of the clock. When SCE is high it is a D latch that is transparent
when C is low. SET is asynchronous and active low.
Logic Symbol
SLF02x
D SQ
C
SD
SE
SCE
Truth Table
SN C D SD SE SCE Q
HHXL LH
HLXL L L
H XHH L H
HXLHL L
H L X X X L NC
HLHX LHH
HL LXLHL
HL XHHHH
HL X LHHL
H H X X X H NC
L XXXXXH
NC = No Change
HDL Syntax
Verilog .................... SLF02x inst_name (Q, C, D, SCE, SD, SE, SN);
VHDL...................... inst_name:SLF02x port map (Q, C, D, SCE, SD, SE, SN);
Pin Loading
Pin Name
C
D
SD
SE
SCE
SN
SLF021
1.0
1.0
1.0
2.2
2.1
2.1
Equivalent Loads
SLF022
SLF024
1.0 1.0
1.0 1.0
1.0 1.0
2.2 2.2
2.2 2.2
2.1 2.1
SLF026
1.0
1.0
1.0
2.2
2.1
2.1
3-226




AMI

SLF024 Datasheet Preview

SLF024 Datasheet

CMOS Gate Array

No Preview Available !

6/)[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
SLF021
13.0
TBD
29.9
SLF022
16.0
TBD
35.2
SLF024
16.0
TBD
38.1
SLF026
17.0
TBD
40.3
a. See page 2-15 for power equation.
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
SLF021
From: C
To: Q
From: D
To: Q
From: SCE
To: Q
From: SD
To: Q
From: SE
To: Q
From: SN
To: Q
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
1.15
1.39
0.94
1.28
0.91
1.01
0.95
1.24
1.01
1.41
0.55
0.74
4
1.26
1.53
1.05
1.42
1.01
1.14
1.05
1.38
1.12
1.55
0.65
0.94
8
1.39
1.68
1.17
1.57
1.13
1.29
1.17
1.53
1.24
1.70
0.77
1.19
13 17 (max)
1.52 1.62
1.84 1.95
1.31 1.41
1.73 1.85
1.28 1.39
1.45 1.57
1.32 1.43
1.69 1.81
1.38 1.49
1.86 1.97
0.92 1.04
1.50 1.74
3-227


Part Number SLF024
Description CMOS Gate Array
Maker AMI
Total Page 5 Pages
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