TD02 - CMOS Gate Array

AMI

General Description

TD0x is a family of non-inverting time delays.

TD02 cmos gate array by AMI - Datasheet Preview

Datasheet Details

Part number	TD02
Manufacturer	AMI
File Size	22.46 KB
Description	CMOS Gate Array
Datasheet	TD02 Datasheet

Full PDF Text Transcription for TD02 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for TD02. For precise diagrams, and layout, please refer to the original PDF.

Core Logic 7'[ $0,+* PLFURQ &026 *DWH $UUD Description TD0x is a family of non-inverting time delays. Logic Symbol Truth Table TD0x Delay AQ LL HH HDL Syntax Verilo...

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delays. Logic Symbol Truth Table TD0x Delay AQ LL HH HDL Syntax Verilog .................... TD0x inst_name (Q, A); VHDL...................... inst_name: TD0x port map (Q, A); Pin Loading Pin Name A TD02 1.5 Equivalent Loads TD03 1.0 TD08 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TD02 9.0 TBD 20.9 TD03 9.0 TBD 22.8 TD08 17.0 TBD 48.4 a. See page 2-15 for power equation. ® 3-236 7'[ ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 TD02 From: A To: Q tPLH tPHL 2.62 2.

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