A48P4616 Datasheet 16M X 16 Bit DDR DRAM

Manufacturer: AMIC Technology

A48P4616 16m x 16 bit ddr dram by AMIC Technology - Datasheet Preview

Datasheet Details

Part number	A48P4616
Manufacturer	AMIC Technology
File Size	2.10 MB
Description	16M X 16 Bit DDR DRAM
Datasheet	A48P4616 Datasheet

General Description

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Overview

www.DataSheet4U.com A48P4616 Preliminary Document Title 16M X 16 Bit DDR DRAM Revision History Rev.

No.

0.0 16M X 16 Bit DDR DRAM History Initial issue Issue Date September 5, 2005 Remark Preliminary Preliminary (September, 2005, Version 0.0) AMIC Technology, Corp.

Key Features

CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5T) 166 200 DDR333 (6K) 133 166 DQS is edge-aligned with data for reads and is centeraligned with data for writes. Differential clock inputs (CK and CK) Four internal banks for concurrent operation. Data mask (DM) for write data. DLL aligns DQ and DQS transitions with CK transitions. Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS. Burst lengths: 2, 4, or 8 CAS La.

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