Datasheet4U Logo Datasheet4U.com

A48P4616B - 16M x 16 Bit DDR DRAM

Datasheet Summary

Description

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.

Features

  • CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5) 133 166 200.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is centeraligned with data for writes.
  • Differential clock inputs (CK and CK ).
  • Four internal banks for concurrent op.

📥 Download Datasheet

Datasheet preview – A48P4616B

Datasheet Details

Part number A48P4616B
Manufacturer AMIC Technology
File Size 1.45 MB
Description 16M x 16 Bit DDR DRAM
Datasheet download datasheet A48P4616B Datasheet
Additional preview pages of the A48P4616B datasheet.

📁 Similar Datasheet

  • A48P3616B - 8M x 16-Bit DDR DRAM (AMIC)
  • A4804 - HIGH-PRECISION N-CH LOW VOLTAGE DETECTOR (AiT Semiconductor)
  • A4805 - HIGH VOLTAGE HIGH PRECISION VOLTAGE DETECTOR (AiT Semiconductor)
  • A4806 - LOW VOLTAGE DETECTOR (AiT Semiconductor)
  • A4809 - LOW VOLTAGE DETECTOR (AiT Semiconductor)
  • A4810A - ULTRA-LOW VOLTAGE DETECTOR (AiT Semiconductor)
  • A4810B - ULTRA-LOW VOLTAGE DETECTOR (AiT Semiconductor)
  • A4811A - LOW VOLTAGE DETECTOR (AiT Semiconductor)
  • A4812 - VOLTAGE DETECTOR (AiT Semiconductor)
  • A489 - 2SA489 (SavantIC)
Other Datasheets by AMIC Technology

Full PDF Text Transcription

Click to expand full text
Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. History 1.0 Initial issue A48P4616B 16M X 16 Bit DDR DRAM Issue Date January 9, 2014 Remark Final (January, 2014, Version 1.0) AMIC Technology, Corp. A48P4616B 16M X 16 Bit DDR DRAM Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5) 133 166 200 „ Double data rate architecture: two data transfers per clock cycle. „ Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver. „ DQS is edge-aligned with data for reads and is centeraligned with data for writes. „ Differential clock inputs (CK and CK ) „ Four internal banks for concurrent operation. „ Data mask (DM) for write data.
Published: |