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A48P4616 - 16M X 16 Bit DDR DRAM

General Description

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.

Key Features

  • CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5T) 166 200 DDR333 (6K) 133 166 DQS is edge-aligned with data for reads and is centeraligned with data for writes. Differential clock inputs (CK and CK) Four internal banks for concurrent operation. Data mask (DM) for write data. DLL aligns DQ and DQS transitions with CK transitions. Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS. Burst lengths: 2, 4, or 8 CAS La.

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Datasheet Details

Part number A48P4616
Manufacturer AMIC Technology
File Size 2.10 MB
Description 16M X 16 Bit DDR DRAM
Datasheet download datasheet A48P4616 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com A48P4616 Preliminary Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. 0.0 16M X 16 Bit DDR DRAM History Initial issue Issue Date September 5, 2005 Remark Preliminary Preliminary (September, 2005, Version 0.0) AMIC Technology, Corp. www.DataSheet4U.com A48P4616 Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5T) 166 200 DDR333 (6K) 133 166 DQS is edge-aligned with data for reads and is centeraligned with data for writes. Differential clock inputs (CK and CK) Four internal banks for concurrent operation. Data mask (DM) for write data. DLL aligns DQ and DQS transitions with CK transitions. Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS.