A48P4616 Datasheet | AMIC Technology

.. Preliminary Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. 16M X 16 Bit DDR DRAM History Initial issue Issue Date September 5, 2005 Remark Preliminary Preliminary (September, 2005, Version 0.0) AMIC Technology, Corp. .. Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5T) 166 200 DDR333 (6K) 133 166 DQS is edge-aligned with data for reads and is centeraligned with data for writes. Differential clock inputs (CK and CK) Four internal banks for concurrent operation. Data mask (DM) for write data. DLL aligns DQ and DQS transitions with CK transitions. mands...