A67P0636 Datasheet | AMIC Technology

.. A67P1618/A67P0636 Series Preliminary Document Title 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 0.1 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Error Correction: delete BWE pin in block diagram Issue Date March 25, 2004 August 6, 2004 Remark Preliminary PRELIMINARY (July, 2004, Version 0.1) AMIC Technology, Corp. A67P1618/A67P0636 Series Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable...