A67P0636A Datasheet PDF | AMIC Technology

AMIC Technology A67P0636A

The A67P1618A, A67P0636A SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers.

Part No.	A67P0636A
Datasheet	A67P0636A Download
Manufacturer	AMIC Technology
Description	SRAM
Buy	Stock & Price

FEATURES

Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package Industrial operating temperature range: -25°C to +85°C for -I series All Pb-free (Lead-free) products are RoHS compliant

GENERAL DESCRIPTION

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The synchronous inputs include all address, all data inputs, active low ch...