Datasheet4U Logo Datasheet4U.com

A67P1618 - (A67P0636 / A67P1618) Pipelined ZeBL SRAM

Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P1618, A67P0636 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

Features

  • Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined.

📥 Download Datasheet

Datasheet preview – A67P1618

Datasheet Details

Part number A67P1618
Manufacturer AMIC Technology
File Size 296.38 KB
Description (A67P0636 / A67P1618) Pipelined ZeBL SRAM
Datasheet download datasheet A67P1618 Datasheet
Additional preview pages of the A67P1618 datasheet.

📁 Similar Datasheet

  • A67-1 - Cascadable Amplifier (MACOM)
  • A6700 - LOW DROPOUT VOLTAGE REGULATOR (AiT Semiconductor)
  • A671 - 2SA671 (Wing Shing Computer Components)
  • A6727 - Single-phase PWM controller (STMicroelectronics)
  • A6727B - Automotive single-phase PWM controller (STMicroelectronics)
  • A673 - 2SA673 (Hitachi Semiconductor)
  • A675 - PNP SILICON TRANSISTOR (NEC)
Other Datasheets by AMIC Technology
  • A67P16181 - (A67P06361 / A67P16181) Flow-through ZeBL SRAM
  • A67P1618A - SRAM
  • A67P0618 - (A67P0618 / A67P9336) Pipelined ZeBL SRAM
  • A67P06181 - (A67P06181 / A67P93361) Flow-through ZeBL SRAM
  • A67P0636 - (A67P0636 / A67P1618) Pipelined ZeBL SRAM
  • A67P06361 - (A67P06361 / A67P16181) Flow-through ZeBL SRAM
  • A67P0636A - SRAM
  • A67P7336 - (A67P8318 / A67P7336) Pipelined ZeBL SRAM

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com A67P1618/A67P0636 Series Preliminary Document Title 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 0.1 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Error Correction: delete BWE pin in block diagram Issue Date March 25, 2004 August 6, 2004 Remark Preliminary PRELIMINARY (July, 2004, Version 0.1) AMIC Technology, Corp. A67P1618/A67P0636 Series Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.
Published: |