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A67P16181 - (A67P06361 / A67P16181) Flow-through ZeBL SRAM

This page provides the datasheet information for the A67P16181, a member of the A67P06361 (A67P06361 / A67P16181) Flow-through ZeBL SRAM family.

Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P16181, A67P06361 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

Features

  • Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined.

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Datasheet preview – A67P16181

Datasheet Details

Part number A67P16181
Manufacturer AMIC Technology
File Size 269.68 KB
Description (A67P06361 / A67P16181) Flow-through ZeBL SRAM
Datasheet download datasheet A67P16181 Datasheet
Additional preview pages of the A67P16181 datasheet.

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Other Datasheets by AMIC Technology
  • A67P1618 - (A67P0636 / A67P1618) Pipelined ZeBL SRAM
  • A67P1618A - SRAM
  • A67P0618 - (A67P0618 / A67P9336) Pipelined ZeBL SRAM
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  • A67P0636 - (A67P0636 / A67P1618) Pipelined ZeBL SRAM
  • A67P06361 - (A67P06361 / A67P16181) Flow-through ZeBL SRAM
  • A67P0636A - SRAM
  • A67P7336 - (A67P8318 / A67P7336) Pipelined ZeBL SRAM

Full PDF Text Transcription

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www.DataSheet4U.com A67P16181/A67P06361 Series Preliminary Document Title 2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 0.1 2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM History Initial issue Error Correction: delete BWE pin in block diagram Issue Date March 25, 2004 August 6, 2004 Remark Preliminary PRELIMINARY (August, 2004, Version 0.1) AMIC Technology, Corp. A67P16181/A67P06361 Series Preliminary Features Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.
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