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A67P7336 - (A67P8318 / A67P7336) Pipelined ZeBL SRAM

This page provides the datasheet information for the A67P7336, a member of the A67P8318 (A67P8318 / A67P7336) Pipelined ZeBL SRAM family.

Datasheet Summary

Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P8318, A67P7336 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

Features

  • Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined.

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Datasheet preview – A67P7336

Datasheet Details

Part number A67P7336
Manufacturer AMIC Technology
File Size 282.20 KB
Description (A67P8318 / A67P7336) Pipelined ZeBL SRAM
Datasheet download datasheet A67P7336 Datasheet
Additional preview pages of the A67P7336 datasheet.

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Other Datasheets by AMIC Technology
  • A67P73361 - (A67P73361 / A67P83181) Flow-through ZeBL SRAM
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  • A67P06361 - (A67P06361 / A67P16181) Flow-through ZeBL SRAM
  • A67P0636A - SRAM
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Full PDF Text Transcription

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www.DataSheet4U.com A67P8318/A67P7336 Preliminary Document Title 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A67P8318/A67P7336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.
Published: |