A67P9318 Datasheet | AMIC Technology

.. A67P9318/A67P8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A67P9318/A67P8336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data...