LP62S1024AX-55LLT Datasheet | AMIC Technology

Features n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30m A(max.) (55NS)40m A(max.) Standby:5u A (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-patible n mon I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) forward type and 36-pin CSP packages General Description The LP62S1024A-T is a low operating current 1,048,576bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOP n TSOP/TSSOP n CSP (Chip Size Package) 36-pin Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 32 31 30 29 28 VCC A15 CE2 WE A13 A B C D E F G H 17 32 1 A0 I/O5 I/O6 GND VCC I/O7 I/O8 A9 OE A10 NC CE1 A11 NC A16 A12 A15 A13 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC GND I/O3 I/O4 A14 16 1 LP62S1024AV-T (LP62S1024AX-T) LP62S1024AM-T 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 WE 21 I/O1 6 CE2 22 I/O 2 7 A15 23 I/O 3 8 VCC 24 GND 9 NC 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O 7 13 A7 29 I/O 8 14 A6 30 CE1 15 A5 31 A10 16 A4 32 OE (August, 2001, Version 1.0) AMIC Technology, Inc. LP62S1024A-T Series Block Diagram A0 VCC GND A14 A15 A16 ROW DECODER 512 X 2048 MEMORY...