LP62S16256G Datasheet | AMIC Technology

.. LP62S16256G-T Series Preliminary Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 History Initial issue Change temperature from 0°C-70°C to -10°C-70°C Issue Date June 6, 2006 November 17, 2006 Remark Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (November, 2006, Version 0.1) AMIC Technology, Corp. .. LP62S16256G-T Series Preliminary Features - Operating voltage: 2.7V to 3.6V - Access times: 55ns / 70ns (max.) - Current: Very low power version: Operating: 40m A (max.) Standby: 10µA (max.) - Full static operation, no clock or refreshing required - All inputs and outputs are directly TTL-patible - mon I/O using three-state output - Data retention voltage: 2.0V (min.) - Available in 44-pin TSOP and 48-ball CSP (6 × 8mm) packages - All Pb-free (Lead-free) products are Ro HS pliant 256K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The LP62S16256G-T is a low operating current 4,194,304-bit static random access memory organized as 262,144 words by 16 bits and operates on low power voltage from 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family Operating Temperature -10°C ~ +70°C VCC Range 2.7V~3.6V Speed Power Dissipation Standby Operating Data Retention (ISB1, Typ.) (ICC2, Typ.) (ICCDR, Typ.) 0.08µA 1µA 2.3m A Package Type 44L TSOP 48B CSP LP62S16256G-T 55ns / 70ns 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC =...