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AMIS-710651-A4 Datasheet Preview

AMIS-710651-A4 Datasheet

CIS Module

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AMIS-710651-A4: Color CIS Module
Data Sheet
1.0 Description
The AMIS-710651-A4 (PI651MC-A4C) is a color contact image sensor (CIS) module. The module contains 15 image-sensor chips,
AMIS-720058 (PI6058E), a product of AMI Semiconductor. These chips are sequentially cascaded to provide a line array of photo-
detectors. Each photo-detector in the image sensor possesses its own independent processing circuit. As the photo-sensors’ digital
shift register scans the image sensor chip, it sequentially produces the video signals at the output of the image array. The AMIS-
710651-A4’s mechanical outline drawing is shown in Figure 6.
2.0 Key Features
600 and 300dpi selectable resolutions
23.6dpm and 11.8dpm, 216mm scanning length
344 or 172 image sensor elements (pixels)
Low power-single power supply at 3.3V
Light source, lens and sensor are integrated into a single module
High speed page scan - up to 1.30msec/line @ 4MHz pixel rate
Analog output
RGB color LED light source
Compact size 12.3mm x 18.9mm x 23mm
Light weight
3.0 Overview
The AMIS-710651-A4 has a 216mm read width. Its minimum line rate is 1.30ms/line with a maximum clock pulse (CP) equal to 4.0MHz
(pixel rate (PRATE) of 4.0MHz). Unless stated otherwise, all data was taken with CP = 3.0MHz (PRATE = 3.0MHz) and an integration
time of 1.75ms/line. The sensor photo-site density is 23.64elements/mm. The module has one analog video output, two clock inputs,
clock and start pulse (CP and SP), one reference voltage input for the amplifier output bias level control, one power supply input and
four LED inputs.
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4.0 Scan Overview
Table 1 describes a scan overview.
Table 1: Scan Overview
Parameter
Specification
Note
Read width
216mm
Sensor photo-site density
42.3 elements/mm
600dpi
84.7 elements/mm
300dpi
Active photo elements
Line read time (1)
Clock frequency (1)
Pixel rate (1)
5160 elements
~ 1.30ms/line
4.0MHz
4.0MHz
Tested @ 4.0MHz (PRATE)
Max. rate
Max. rate
Note:
Since the light power is fixed, if the line-scan rate is set proportional to the clock rate, then the integration time reduces as the clock frequency is increased, hence its
exposure. The reduction in the exposure proportionately reduces the video output. Accordingly, the signal-to-noise ratio reduces as the frequency increased.
AMI Semiconductor – Aug. 06, M-20609-001
www.amis.com
1




AMI SEMICONDUCTOR

AMIS-710651-A4 Datasheet Preview

AMIS-710651-A4 Datasheet

CIS Module

No Preview Available !

AMIS-710651-A4: Color CIS Module
Data Sheet
5.0 Physical Overview
Table 2 describes a physical overview.
Table 2: Physical Overview
Parameter
Image sensors
Module outside dimension
Circuit power supply
Data output
Specification
A<OS-720058
12.3mm x 18.9mm x 232mm
Typical 3.3V @ 70mA
One analog output
Note
See image sensor data sheet
Figure 6
6.0 Recommended Operating Conditions
All tests were conducted at the typical pixel rate of 3.0MHz
Table 3: Recommended Operating Conditions (25°C)
Parameter
Symbol
Min.
Typ.
Max.
Units
Power supply
VDD
3.3 V
Video output level
Reference voltage input
IDD
VP (1)
VREF (2)
0.15
70 100 mA
0.2 V
1.2 V
Input voltage for digital high (input clocks, SP
VIH
3.2
VDD
VDD +0.3
V
and CP)
Input voltage for digital low (input clocks SS
VIL
0
0.8 V
and CP)
Clock frequency
Pixel frequency
Clock pulse high duty cycle
FREQ (3)
PRATE (3)
DUTY (4)
0.50
0.50
3.0 4.0 MHz
3.0 4.0 MHz
50 %
Clock pulse high duration
Integration time
Operating temperature
TPW
TINT (5)
TOP (6)
200
~1300
ns
10000
µs
25 50 °C
Notes:
www.Da(1t)aShVePerte4pUre.csoemnts the average value Vp(n) for all n in line scans, where n is the sequential number of a pixel. This signal pixel level should be operated at less than
saturation levels, i.e., <1.3V.
(2) VREF is used to adjust the video output bias. Under normal operation it is left unconnected.
(3) FREQ is the input clock (CP) frequency and the pixel rate (PRATE). The minimum rate for FREQ and PRATE should be consistent with the maximum TINT, see
Note (5).
(4) DUTY is the ratio of the clock’s pulse width to its pulse period.
(5) TINT is the time interval between two start pulses (SP). Hence, if SP is generated from a clock count down circuit, it will be directly proportional to the clock
frequency. There must be a minimum of (56+1204) clock cycles between the two SPs. The longest integration time is determined by the degree of leakage current
degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the
desired leakage tolerance level for the given system.
(6) TOP is a conservative engineering estimate. It is based on measurements of similar CIS modules. In production, they are measured under standard QA practices,
that is, under the control of ISO 9000 standards.
AMI Semiconductor – Aug. 06, M-20609-001
www.amis.com
2


Part Number AMIS-710651-A4
Description CIS Module
Maker AMI SEMICONDUCTOR
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