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AT32F402 - 32-bit MCU

This page provides the datasheet information for the AT32F402, a member of the AT32F405 32-bit MCU family.

Datasheet Summary

Description

10 2 Functionality overview 13 2.1 ARM®Cortex®-M4 with FPU 13 2.2 Memory 13 2.2.1 Internal Flash memory 13 2.2.2 Memory protection unit (MPU) 13 2.2.3 SRAM 13 2.2.4 Quad SPI interface (QSPI)14 2.3 Interrupts 14

Features

  • Core: ARM® 32-bit Cortex®-M4 CPU with FPU.
  • 216 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division.
  • Floating point unit (FPU).
  • DSP instructions.
  • Memories.
  • 128 to 256 Kbytes of Flash memory.
  • 20 Kbytes of boot memory used as a Bootloader or as a general instruction/data memory (one-time programmable).
  • sLib: configurable part of main Flash as a library area with code executabl.

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Datasheet preview – AT32F402

Datasheet Details

Part number AT32F402
Manufacturer ARTERY
File Size 2.48 MB
Description 32-bit MCU
Datasheet download datasheet AT32F402 Datasheet
Additional preview pages of the AT32F402 datasheet.
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Full PDF Text Transcription

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AT32F405/402 Series Datasheet ARM®-based 32-bit Cortex®-M4 MCU with FPU, 128 to 256 KB Flash, sLib, 14 timers, 1 ADC, 19 communication interfaces (CAN, OTGHS, OTGFS) Features  Core: ARM® 32-bit Cortex®-M4 CPU with FPU − 216 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division − Floating point unit (FPU) − DSP instructions  Memories − 128 to 256 Kbytes of Flash memory − 20 Kbytes of boot memory used as a Bootloader or as a general instruction/data memory (one-time programmable) − sLib: configurable part of main Flash as a library area with code executable but secured, non-readable − 70 to 102 Kbytes of SRAM (the first 48 KB with parity check) − QSPI interface for interfacing external SPI memory or SPI RAM extension, supporting add
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