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AT17C65 - FPGA Configuration EEPROM Memory

Description

The AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 Series) FPGA configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays.

Features

  • EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs).
  • In-System Programmable (ISP) via 2-wire Bus.
  • Simple Interface to SRAM FPGAs.
  • Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™ Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex™ FPGAs, Motorola MPA1000 FPGAs.
  • Cascadable Read-back to Su.

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Other Datasheets by ATMEL Corporation
  • AT17C65A - FPGA Configuration EEPROM
  • AT17C010 - FPGA Configuration E2PROM Memory
  • AT17C010A - FPGA Serial Configuration Memories
  • AT17C128 - FPGA Configuration EEPROM Memory
  • AT17C128A - FPGA Configuration EEPROM
  • AT17C256 - FPGA Configuration EEPROM Memory
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Full PDF Text Transcription

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Features • EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • In-System Programmable (ISP) via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™ Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex™ FPGAs, Motorola MPA1000 FPGAs • Cascadable Read-back to Support Additional Configurations or Higher-density Arrays • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP, 8-lead SOIC and 20-lead PLCC Packages (Pin Compatible Across Product Family) • Emulation of Atmel’s AT24C
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