ATR0663
Key Features
- Incorporates the ARM926EJ-S™ ARM® Thumb® Processor - DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration - 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer - 220 MIPS at 200 MHz (1.1 MIPS/MHz) - Memory Management Unit - Embedded ICE In-circuit Emulation, Debug Communication Channel Support - Mid-level Implementation Embedded Trace Macrocell™ GPS Engine - GPS Engine with Massive Parallel Correlation - Highest Acquisition and Tracking Sensitivity - Fast Time To First Fix (TTFF) - SBAS Support (WAAS, EGNOS) - NMEA 2.2 Data Format Bus Matrix - Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth - Addresses Internal and External Memories Embedded Memories - One 128-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed - One 80-Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Matrix Speed - One 16-Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed Dual External Bus Interface (EBI0 and EBI1) - Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® LCD Controller - Supports Passive or Active Displays - Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode, Resolution up to 2048× 2048, Supports Wider Screen Buffers 2D Graphics Accelerator - Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing Image Sensor Interface - ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors 4× 4 Keypad Matrix Controller USB 2.0 Full-speed (12 Mbits per Second) Host Double Port and Device Port Ethernet MAC 10/100 Base T One Part 2.0A and Part 2.0B Compliant CAN Controller Two Multimedia Card Interfaces (MCI) Two Synchronous Serial Controllers (SSC) Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) Two Master/Slave Seri
