T89C5115
Overview
- 80C51 Core Architecture
- 256 Bytes of On-chip RAM
- 256 Bytes of On-chip XRAM
- 16K Bytes of On-chip Flash Memory - Data Retention: 10 Years at 85°C - Erase/Write Cycle: 100K
- 2K Bytes of On-chip Flash for Bootloader
- 2K Bytes of On-chip EEPROM - Erase/Write Cycle: 100K
- 14-sources 4-level Interrupts
- Three 16-bit Timers/Counters
- Full Duplex UART Compatible 80C51
- Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
