TSXPC603R
Features
- -
- -
- -
- Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit patibility Power PC Implementation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Offered in Cerquad, CBGA 255, Hi TCE CBGA 255 and CI-CGA 255
Features
Specific to CBGA 255, Hi TCE CBGA 255 and CI-CGA 255
- -
- -
- -
- -
- -
- 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated) PD Typically = 3.5W (266 MHz), Full Operating Conditions Branch Folding 64-bit Data Bus (32-bit Data Bus Option) 4-Gbytes Direct Addressing Range Pipelined Single/Double Precision Float Unit IEEE 754 patible FPU IEEE P 1149-1 Test Mode (JTAG/C0P) f INT Max = 300 MHz f BUS Max = 75 MHz patible CMOS Input/TTL Output
Power PC® 603e RISC Microprocessor Family PID7t-603e TSPC603R
Features
Specific to Cerquad
- 5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
- PD Typically = 2.5W (200 MHz), Full Operating Conditions
1. Description
The PID7t-603e implementation of the Power PC 603e...
