HCTL-2021 Datasheet | AVAGO TECHNOLOGIES

.. HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs Data Sheet Description The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS patible tri-state output buffers. Operation is specified for a temperature range from - 40 to +85°C at clock frequencies up to 33MHz. The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard puter ICs. The HCTL-2021/2017 is pliant to Ro HS directive and had been declared as a lead free product. Features - Interfaces Encoder to Microprocessor - 33 MHz Clock Operation - High Noise Immunity: Schmitt Trigger Inputs and Digital Noise Filter - 16-Bit Binary Up/Down Counter - Latched Outputs - 8-Bit Tristate Interface - 8 or 16-Bit Operating Modes - Quadrature Decoder Output Signals, Up/Down and Count - Cascade Output Signals, Up/Down and Count - Substantially Reduced System Software - 5V Operation (VDD - VSS) - TTL/CMOS patible I/O - Operating Temperature: -40°C to 85°C - 16-pin and 20-Pin Launch Pad Applications - Interface Quadrature Incremental Encoders to Microprocessors - Interface Digital Potentiometers to Digital Data Input Buses Devices Part Number HCTL-2017 HCTL-2021 Description 33 MHz clock operation. 16-bit counter. 33 MHz clock operation. 16-bit counter. Quadrature decoder output signals. Cascade output signals. Pinout PINOUT A PINOUT B .Data...