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UT54ACTS163 Datasheet Preview

UT54ACTS163 Datasheet

4-Bit Synchronous Counters

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Standard Products
UT54ACS163/UT54ACTS163
4-Bit Synchronous Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Internal look-ahead for fast counting
‰ Carry output for n-bit cascading
‰ Synchronous counting
‰ Synchronously programmable
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS163 - SMD 5962-96554
‰ UT54ACTS163 - SMD 5962-96555
DESCRIPTION
The UT54ACS163 and the UT54ACTS163 are synchronous
presettable 4-bit binary counters that feature internal carry look-
ahead logic for high-speed counting designs. Synchronous op-
eration occurs by having all flip-flops clocked simultaneously
so that the outputs change coincident with each other when in-
structed by the count-enable inputs and internal gating. A buff-
ered clock input triggers the four flip-flops on the rising (posi-
tive-going) edge of the clock input waveform.
The counters are fully programmable (i.e., they may be preset
to any number between 0 and 15). Presetting is synchronous;
applying a low level at the load input disables the counter and
causes the outputs to agree with the load data after the next clock
pulse.
The clear function is synchronous and a low level at the clear
input sets all four of the flip-flop outputs low after the next clock
pulse. This synchronous clear allows the count length to be mod-
ified by decoding the Q outputs for the maximum count desired.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, or LOAD) that modify the operat-
ing mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
PINOUTS
16-Pin DIP
Top View
CLR
CLK
A
B
C
D
ENP
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
RCO
QA
QB
QC
QD
ENT
LOAD
CLR
CLK
A
B
C
D
ENP
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
RCO
QA
QB
QC
QD
ENT
LOAD
LOGIC SYMBOL
(1)
CLR
(9)
LOAD
ENT
ENP
CLK
(10)
(7)
(2)
CTRDIV 16
5CT=0
M1
M2 3CT = 15
G3
G4
C5/2,3,4+
(3)
A
(4)
B
(5)
C
(6)
D
1,5D
(1)
(2)
(4)
(8)
(15) RCO
(14) QA
(13) QB
(12) QC
(11) QD
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-
cation 617-12.
1




Aeroflex Circuit Technology

UT54ACTS163 Datasheet Preview

UT54ACTS163 Datasheet

4-Bit Synchronous Counters

No Preview Available !

FUNCTION TABLE
Operating Mode CLR
Reset (Clear)
Parallel Load
Count
Inhibit
l
h3
h3
h3
h3
h3
CLK
X
X
ENP
X
X
X
h
l2
X
ENT
X
X
X
h
X
l2
LOAD
X
l
l
h
h3
h3
DATA A,B,C,D
X
l
h
X
X
X
H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition
L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition
Notes:
1. The RCO output is high when ENT is high and the counter is at terminal count HHHH.
2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations.
3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations.
LOGIC DIAGRAM
QN RCO
LL
LL
H1
Count 1
QN 1
QN L
(2)
CLK
CLR (1)
LOAD (9)
ENP (7)
(10)
ENT
(3)
DATA A
(4)
DATA B
DQ
C
Q
(14) QA
DQ
C
Q
(13) QB
(5)
DATA C
DQ
C
Q
(12) QC
(6)
DATA D
DQ
C
Q
(11) QD
(15) RCO
2



Part Number UT54ACTS163
Description 4-Bit Synchronous Counters
Maker Aeroflex Circuit Technology
Total Page 10 Pages
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UT54ACTS163 Datasheet PDF





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