Description
1
TEST
PE/HD
FS
VDDQ1
PD/DIV XTAL1
3 3 /R 3 3 LOCK
NC/XTAL2 PLL /N 3 3
FB
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DS[1:0] 3 1F[1:0] 3 1Q0 Phase Select 1Q1
3 2F[1:0] 3
Phase Select
2Q0 2Q1
3 3F[1:0] 3
Phase Select and /K
3Q0
3Q1 VDDQ3
3 4F[1:0] 3
Phase Select and /M
4Q0 4Q1
VDDQ4 Figure 2. UT7R995 & UT7R995C Block Diagram
sOE
2
1.0 DEVICE CONFIGURATION: The outputs of the UT7R995/C can be configured to run at frequencies ranging from 6 MHz to 200 MHz.Each output bank has the ability to run a
Features
- +3.3V Core Power Supply +2.5V or +3.3V Clock Output Power Supply Independent Clock Output Bank Power Supplies www. DataSheet4U. com Output frequency range: 6 MHz to 200 MHz Bank pair output-output skew < 100 ps Cycle-cycle jitter < 50 ps 50% ± 2% maximum output duty cycle at 100MHz Eight LVTTL outputs with selectable drive strength Selectable positive- or negative-edge synchronization Selectable phase-locked loop (PLL) frequency range and lock indicator Phase adjustments in 625 to 1300 ps steps u.