A3950 Datasheet | Allegro MicroSystems

FEATURES AND BENEFITS - Low RDS(on) outputs - Overcurrent protection - Motor lead short-to-supply protection - Short-to-ground protection - Sleep function - Synchronous rectification - Diagnostic output - Internal undervoltage lockout (UVLO) - Crossover-current protection PACKAGES: Package LP, 16-pin TSSOP with Exposed Thermal Pad DMOS Full-Bridge Motor Driver DESCRIPTION Designed for PWM (pulse-width modulated) control of DC motors, the A3950 is capable of peak output currents to ±2.8 A and operating voltages to 36 V. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. Internal circuit protection includes motor lead short-tosupply / short-to-ground, thermal shutdown with hysteresis, undervoltage monitoring of VBB and VCP, and crossover-current protection. The A3950 is supplied in a thin profile (<1.2 mm overall height) 16-pin TSSOP package (LP), and a very thin (0.75 mm nominal height) QFN package. Both packages provide an exposed pad for enhanced thermal dissipation, and are lead (Pb) free with 100% matte tin leadframe plating. Package EU, 16-pin QFN with Exposed Thermal Pad Not to scale VDD 5 kΩ Typical Application Diagrams 0.22 µF 25 V VBB 0.1 µF 50 V MODE NFAULT VREG VCP PHASE GND SLEEP ENABLE CP2 A3950 EU Package CP1 OUTB 0.1 µF 50 V 100 µF 50 V NC OUTA SENSE VBB 0.1 µF 50 V VDD 5...