AS4C128M16D3LB-12BIN Datasheet PDF - Alliance Semiconductor 2G DDR3L Specs

AS4C128M16D3LB-12BIN - 2G DDR3L

Datasheet Summary

Features

JEDEC Standard Compliant.
Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V).
Backward compatible to VDD & VDDQ = +1.5V ±0.075V.
Operating temperature: TC = -40~95°C (Industrial).
Supports JEDEC clock jitter specification.
Fully synchronous operation.
Fast clock rate: 800MHz.
Differential Clock, CK & CK#.
Bidirectional differential data strobe - DQS & DQS#.
8 internal banks for concurrent operation.
8n-bit prefetch architecture.
Pipel.

Datasheet Details

Part number	AS4C128M16D3LB-12BIN
Manufacturer	Alliance Semiconductor
File Size	1.96 MB
Description	2G DDR3L
Datasheet	AS4C128M16D3LB-12BIN Datasheet
Additional preview pages of the AS4C128M16D3LB-12BIN datasheet.

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Full PDF Text Transcription

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AS4C128M16D3LB-12BIN Revision History 2G DDR3L AS4C128M16D3LB-12BIN 96ball FBGA PACKAGE Revision Details Rev 1.0 Preliminary datasheet Date Dec. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 Dec. 2017 AS4C128M16D3LB-12BIN 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Dec. /2017) Features  JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V)  Backward compatible to VDD & VDDQ = +1.5V ±0.

Published: Mar 19, 2019 |