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AS4C128M16D3LC-12BIN - 128M x 16 bit DDR3L Synchronous DRAM

Key Features

  • Overview.
  • JEDEC Standard Compliant The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is.
  • Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V) double data rate architecture to achieve high-speed.
  • Backward compatible to VDD & VDDQ = +1.5V ±0.075V.
  • Operating temperature: - Commercial : TC = 0~95°C operation. It is internally configured as an eight bank DRAM. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed - Industrial :.

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Datasheet Details

Part number AS4C128M16D3LC-12BIN
Manufacturer Alliance Semiconductor
File Size 1.76 MB
Description 128M x 16 bit DDR3L Synchronous DRAM
Datasheet download datasheet AS4C128M16D3LC-12BIN Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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AS4C128M16D3LC-12BIN AS4C128M16D3LC-12BCN Revision History 2Gb AS4C128M16D3LC 96 ball FBGA PACKAGE Revision Details Rev 1.0 Initial Release Date Feb.2020 Alliance Memory Inc. 12815 NE 124th St. STE#D,Kirkland WA 98034 TEL: (425) 898-44356 FAX: (425) 868-8628 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 87 - Rev.1.0 FEB. 2020 AS4C128M16D3LC-12BIN AS4C128M16D3LC-12BCN 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Initial Release (Rev. 1.0, Feb. /2020) Features Overview  JEDEC Standard Compliant The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is  Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V) double data rate architecture to achieve high-speed  Backward compatible to VDD & VDDQ = +1.5V ±0.