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AS7C31024B - 3.3V 128K x 8 CMOS SRAM

Description

The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits.

It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Features

  • Industrial and commercial temperatures.
  • Organization: 131,072 words x 8 bits.
  • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time.
  • Low power consumption: ACTIVE - 252 mW / max @ 10 ns.
  • Easy memory expansion with CE1, CE2, OE inputs.
  • TTL/LVTTL-compatible, three-state I/O.
  • 32-pin JEDEC standard packages 300 mil SOJ 400 mil SOJ 8 × 20mm TSOP 1 8 x 13.4mm sTSOP 1.
  • Low power consumption: S.

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Datasheet preview – AS7C31024B

Datasheet Details

Part number AS7C31024B
Manufacturer Alliance Semiconductor Corporation
File Size 148.88 KB
Description 3.3V 128K x 8 CMOS SRAM
Datasheet download datasheet AS7C31024B Datasheet
Additional preview pages of the AS7C31024B datasheet.

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Full PDF Text Transcription

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March 2004 ® AS7C31024B www.DataSheet4U.com 3.3V 128K X 8 CMOS SRAM Features • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE - 252 mW / max @ 10 ns • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages 300 mil SOJ 400 mil SOJ 8 × 20mm TSOP 1 8 x 13.4mm sTSOP 1 • Low power consumption: STANDBY - 18 mW / max CMOS • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • 6T 0.
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