AS7C33256NTF18B
Features
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- - Organization: 262,144 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package
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- - Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation
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Logic block diagram
A[17:0] 18 D
Address register burst logic
CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ CLK
Q 18
Write delay addr. registers
Control logic
Write Buffer
256K x 18 SRAM array
DQ [a,b]
Data Q input register
18 18 18
18 CLK CEN OE
Output buffer
18 OE
DQ [a,b]
Selection guide
-75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby...
