ASM4SSTVF16859 buffer equivalent, ddr 13-bit to 26-bit registered buffer.
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* Differential clock signals. Meets SSTL_2 class II specifications on outputs.
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LVCMOS level at a valid state since VREF may not be st.
Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive e.
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