on page 1
  –2. Global change from SignalTap to SignalTap II. The DSP blocks in “Features” on page 1
  –2 provide dedicated implementation of m.

; –75. Updated Table 4
  –123 on page 4
  –87. Updated Table 4
  –124 on pag.

on page 2
  –71. Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page 2
  –88. Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page .

EP1S

EP1S-3G1

EP1S-3G1T

EP1S-3G1TT

EP1S-3G2

EP1S-3G2T

EP1S-3G2TT

EP1S-3G3

EP1S-3G3T

EP1S-3G3TT

EP1S-3G4

EP1S-3G4T

EP1S-3G4TT