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EPM3128A - Programmable Logic

Download the EPM3128A datasheet PDF. This datasheet also covers the EPM3032A variant, as both devices belong to the same programmable logic family and are provided as variant models within a single manufacturer datasheet.

General Description

PCI compatible Bus friendly architecture including programmable slew rate control Open drain output option Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power saving mode fo

Key Features

  • High.
  • performance, low.
  • cost CMOS EEPROM.
  • based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1).
  • 3.3-V in-system programmability (ISP) through the built.
  • in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability.
  • ISP circuitry compliant with IEEE Std. 1532.
  • Built.
  • in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990.
  • Enhanced ISP features:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EPM3032A-Altera.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EPM3128A
Manufacturer Altera
File Size 729.56 KB
Description Programmable Logic
Datasheet download datasheet EPM3128A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
June 2006, ver. 3.5 ® MAX 3000A Programmable Logic Device Family Data Sheet Features... ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std. 1532 ■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ■ Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming ■ High–density PLDs ranging from 600 to 10,000 usable gates ■ 4.