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AD5684 - Quad nanoDAC

Download the AD5684 datasheet PDF. This datasheet also covers the AD5686 variant, as both devices belong to the same quad nanodac family and are provided as variant models within a single manufacturer datasheet.

General Description

The AD5686/AD5684, members of the nanoDAC+™ family, are low power, quad, 16-/12-bit buffered voltage output DACs.

The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2).

Key Features

  • High relative accuracy (INL): ±2 LSB maximum @ 16 bits.
  • Tiny package: 3 mm × 3 mm, 16-lead LFCSP.
  • Total unadjusted error (TUE): ±0.1% of FSR maximum.
  • Offset error: ±1.5 mV maximum.
  • Gain error: ±0.1% of FSR maximum.
  • High drive capability: 20 mA, 0.5 V from supply rails.
  • User selectable gain of 1 or 2 (GAIN pin).
  • Reset to zero scale or midscale (RSTSEL pin).
  • 1.8 V logic compatibility.
  • 50 MHz SPI with readback or daisy chain.
  • Low glitch: 0.5 n.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AD5686_AnalogDevices.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Analog Devices

Part Number Description
AD5684R Quad 16-/14-/12-Bit nanoDAC
AD568 12-Bit Ultrahigh Speed Monolithic D/A Converter
AD5680 5V 18-Bit nanoDAC
AD5681R Tiny SPI nanoDAC+
AD5682R Tiny SPI nanoDAC+

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Data Sheet AD5686/AD5684 Quad, 16-/12-Bit nanoDAC+ with SPI Interface FEATURES ► High relative accuracy (INL): ±2 LSB maximum @ 16 bits ► Tiny package: 3 mm × 3 mm, 16-lead LFCSP ► Total unadjusted error (TUE): ±0.1% of FSR maximum ► Offset error: ±1.5 mV maximum ► Gain error: ±0.1% of FSR maximum ► High drive capability: 20 mA, 0.5 V from supply rails ► User selectable gain of 1 or 2 (GAIN pin) ► Reset to zero scale or midscale (RSTSEL pin) ► 1.8 V logic compatibility ► 50 MHz SPI with readback or daisy chain ► Low glitch: 0.5 nV-sec ► Low power: 1.8 mW at 3 V ► 2.7 V to 5.