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Analog Devices Semiconductor Electronic Components Datasheet

AD61009 Datasheet

Low Power Mixer 3V Receiver IF Subsystem

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a
FEATURES
Complete Receiver-on-a-Chip: Monoceiver® Mixer
–15 dBm 1 dB Compression Point
–8 dBm Input Third Order Intercept
500 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB Gain Control
Manual Gain Control
Quadrature Demodulator
On-Board Phase-Locked Quadrature Oscillator
Demodulates IFs from 1 MHz to 12 MHz
Can Also Demodulate AM, CW, SSB
Low Power
25 mW at 3 V
CMOS Compatible Power-Down
APPLICATIONS
GSM and TETRA Receivers
Satellite Terminals
Battery-Powered Communications Receivers
Low Power Mixer
3 V Receiver IF Subsystem
AD61009
PIN CONFIGURATION
20-Lead SSOP
(RS Suffix)
FDIN 1
20 VPS1
COM1 2
19 FLTR
PRUP 3
18 IOUT
LOIP 4
17 QOUT
RFLO 5 AD61009 16 VPS2
RFHI
6
TOP VIEW
(Not to Scale)
15
DMIP
GREF 7
14 IFOP
MXOP 8
13 COM2
VMID 9
12 GAIN
IFHI 10
11 IFLO
GENERAL DESCRIPTION
The AD61009 is a 3 V low power receiver IF subsystem for opera-
tion at input frequencies as high as 500 MHz and IFs from
400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and
Q demodulators, a phase-locked quadrature oscillator, and a
biasing system with external power-down.
The AD61009’s low noise, high intercept mixer is a doubly-
balanced Gilbert cell type. It has a nominal –15 dBm input
referred 1 dB compression point and a –8 dBm input referred
third-order intercept. The mixer section of the AD61009 also
includes a local oscillator (LO) preamplifier, which lowers the
required LO drive to –16 dBm.
In MGC operation, the AD61009 accepts an external gain-
control voltage input from an external AGC detector or a DAC.
A quadrature VCO phase-locked to the IF drives the I and Q
demodulators. The I and Q demodulators can also demodu-
late AM; when the AD61009’s quadrature VCO is phase locked
to the received signal, the in-phase demodulator becomes a
synchronous product detector for AM. The VCO can also be
phase-locked to an external beat-frequency oscillator (BFO),
and the demodulator serves as a product detector for CW or
SSB reception. Finally, the AD61009 can be used to demodu-
late BPSK using an external Costas Loop for carrier recovery.
Monoceiver is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001


Analog Devices Semiconductor Electronic Components Datasheet

AD61009 Datasheet

Low Power Mixer 3V Receiver IF Subsystem

No Preview Available !

AD61009–SPECIFICATIONS (@ TA = 25؇C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted)
Model
DYNAMIC PERFORMANCE
MIXER
Maximum RF and LO Frequency Range
Maximum Mixer Input Voltage
Input 1 dB Compression Point
Input Third-Order Intercept
Noise Figure
Maximum Output Voltage at MXOP
Mixer Output Bandwidth at MXOP
LO Drive Level
LO Input Impedance
Isolation, RF to IF
Isolation, LO to IF
Isolation, LO to RF
Isolation, IF to RF
IF AMPLIFIERS
Noise Figure
Input 1 dB Compression Point
Output Third-Order Intercept
Maximum IF Output Voltage at IFOP
Output Resistance at IFOP
Bandwidth
GAIN CONTROL
Gain Control Range
Gain Scaling
Gain Scaling Accuracy
Bias Current at GAIN
Bias Current at GREF
Input Resistance at GAIN, GREF
I AND Q DEMODULATORS
Required DC Bias at DMIP
Input Resistance at DMIP
Input Bias Current at DMIP
Maximum Input Voltage
Amplitude Balance
Quadrature Error
Phase Noise in Degrees
Demodulation Gain
Maximum Output Voltage
Output Offset Voltage
Output Bandwidth
PLL
Required DC Bias at FDIN
Input Resistance at FDIN
Input Bias Current at FDIN
Frequency Range
Required Input Drive Level
Acquisition Time to ± 3°
Conditions
AD61009ARS
Min Typ
Max
For Conversion Gain > 20 dB
For Linear Operation; Between RFHI and RFLO
RF Input Terminated in 50
RF Input Terminated in 50
Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz
Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz
ZIF = 165 , at Input Compression
–3 dB, ZIF = 165
Mixer LO Input Terminated in 50
LOIP to VMID
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
Max Gain, f = 10.7 MHz
IF = 10.7 MHz
IF = 10.7 MHz
ZIF = 600
From IFOP to VMID
–3 dB at IFOP, Max Gain
(See Figures 10 and 11)
Mixer + IF Section, GREF to 1.5 V
GREF to 1.5 V
GREF to General Reference Voltage VR
GREF to 1.5 V, 80 dB Span
From DMIP to VMID
IF > 3 MHz
IF 3 MHz
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, F = 10 kHz
Sine Wave Input, Baseband Output
RL 20 k
Measured from IOUT, QOUT to VMID
Sine Wave Input, Baseband Output
–3.5
17.4
–100
From FDIN to VMID
Sine Wave Input at Pin 1
IF = 10.7 MHz
500
± 54
–15
–5
14
12
± 1.3
45
–16
1
30
20
40
70
17
–15
18
± 560
15
45
90
20
75/VR
±1
5
1
1
VPOS/2
50
2
±150
±75
± 0.2
–1.2
–100
18
±1.23
10
1.5
+1.5
18.8
+100
VPOS/2
50
200
1.0 to 12
400
16.5
POWER-DOWN INTERFACE
Logical Threshold
Input Current for Logical High
Turn-On Response Time
Standby Current
POWER SUPPLY
Supply Range
Supply Current
OPERATING TEMPERATURE
TMIN to TMAX
For Power Up on Logical High
To PLL Locked
Operation to 2.85 V Minimum Supply Voltage
Operation to 4.5 V Minimum Supply Voltage
2
75
16.5
550
2.85
8.5
–25
–40
5.5
12.5
+85
+85
Specifications subject to change without notice.
–2–
Unit
MHz
mV
dBm
dBm
dB
dB
V
MHz
dBm
k
dB
dB
dB
dB
dB
dBm
dBm
mV
MHz
dB
mV/dB
dB/V
dB
µA
µA
M
V dc
k
µA
mV
mV
dB
Degrees
dBc/Hz
dB
V
mV
MHz
V dc
k
nA
MHz
mV
µs
V dc
µA
µs
µA
V
mA
°C
°C
REV. 0


Part Number AD61009
Description Low Power Mixer 3V Receiver IF Subsystem
Maker Analog Devices
Total Page 24 Pages
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