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AD6121 Datasheet

CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator

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a
CDMA 3 V Receiver IF Subsystem
with Integrated Voltage Regulator
FEATURES
Fully Compliant with IS98A and PCS Specifications
CDMA, W-CDMA, AMPS, and TACS Operation
Linear IF Amplifier
5.9 dB Noise Figure
–47.5 dB to +47 dB Linear-in-dB Gain Control
Quadrature Demodulator
Demodulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
200 mV Voltage Drop
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10 mA at Midgain
<1 A Sleep Mode Operation
Companion Transmitter IF Chip Available (AD6122)
APPLICATIONS
CDMA, W-CDMA, AMPS, and TACS Operation
QPSK Receivers
AD6121
GENERAL DESCRIPTION
The AD6121 is a low power receiver IF subsystem specifically
designed for CDMA applications. It consists of high dynamic
range IF amplifiers with voltage controlled gain, a divide-by-two
quadrature generator, an I and Q demodulator, and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.
The gain control input accepts an external gain control voltage
input from a DAC. It provides 94.5 dB of gain control with a
nominal 52.5 dB/V scale factor when using an internal voltage
reference. The gain control interface reference input can be
connected to either the internal reference or an external reference.
The I and Q demodulator provides differential quadrature base-
band outputs to interface with CDMA baseband converters. A
divide-by-two quadrature generator followed by dual polyphase
filters ensures maximum ± 2.5° quadrature accuracy.
The AD6121 IF Subsystem is fabricated using a 25 GHz ft
BiCMOS silicon process and is packaged in a 28-lead SSOP
and a 32-leadless LPCC chip scale package (5 mm × 5 mm).
FUNCTIONAL BLOCK DIAGRAM
ROOFING
FILTER
CDMA
INPUT
FM
INPUT
IF
OUTPUT
DEMODULATOR
INPUT
IF AMPLIFIERS
INPUT STAGE
PTAT
TEMPERATURE
COMPENSATION
I
2
AD6121
Q
QUADRATURE DEMODULATOR
IOUT
IOUT
LOCAL
OSCILLATOR
INPUT
QOUT
QOUT
GAIN CONTROL
SCALE FACTOR
VREG
LOW
DROPOUT
REGULATOR
VPOS
CDMA/FM
SELECT
GAIN
CONTROL
VOLTAGE
INPUT
POWER- POWER-
GAIN
1.23V DOWN 2 DOWN 1
CONTROL REFERENCE
VOLTAGE OUTPUT
REFERENCE
INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


Analog Devices Semiconductor Electronic Components Datasheet

AD6121 Datasheet

CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator

No Preview Available !

AD6121–SPECIFICATIONS (TA = +25؇C, VCC = 3.0 V, LO = 2 ؋ IF, REFIN = 1.23 V, LDO Enabled, unless otherwise
noted) Note: All power measurements in dBm are referred to 1 kunless ZIN is noted.
Specification
Conditions
Min Typ Max Units
TOTAL GAIN
Maximum Gain
Minimum Gain
IF Amplifiers and Demodulator Powered Up
IF Amplifiers Powered Up and Demodulator Powered Down
IF Amplifier and Demodulator Powered Up
+47
+41.4
–47.5
dB
dB
dB
IF AMPLIFIER
CDMA and FM Input
Noise Figure
Input Third-Order Intercept
Input 1 dB Compression Point
Gain Flatness
CDMA Input Capacitance
CDMA Input Resistance
FM Input Capacitance
FM Input Resistance
Output Capacitance
Output Resistance
IF = 85.38 MHz
Maximum Gain
Maximum Gain
Maximum Gain
IF ± 630 kHz, CDMA Mode
Differential
Differential
Differential
Differential
Differential
Differential
5.9
–42.8
–51.6
± 0.25
2.8
850
2.3
670
1.35
1.1
dB
dBm
dBm
dB
pF
pF
pF
k
GAIN CONTROL INTERFACE
Gain Scaling
Gain Scaling Accuracy
Gain Control Response Time
Input Resistance at REFIN
Input Resistance at VGAIN
DEMODULATOR
Differential Input Impedance
Differential Input Capacitance at
Demodulator Input
Input Third Order Intercept
Demodulation Gain
I/Q Output
Differential Output Voltage
Bandwidth
Resistance
Quadrature Accuracy
Amplitude Balance
LO Input Impedance
LO Input Capacitance
Using Internal Reference
Within a Gain Control Range of 90 dB
Minimum Gain to Maximum Gain
LO = 172.76 MHz , –15 dBm Referred to 50 ,
Baseband Frequency = 1 MHz
10 k, 2 pF Differential Parallel Load Impedance
–3 dB
Single-Ended
Differential
Differential
52.5 dB/V
± 3 dB/V
695 ns
10 M
100 k
1 k
2.9 pF
–6.1 dBm
5.6 dB
700 mV p-p
16 MHz
630
± 2.5 Degree
± 0.1 ± 0.35 dB
1.5 k
4.16 pF
CONTROL INTERFACES
Logic Threshold High
Logic Threshold Low
Input Current for Logic High
Mode Control Response Time
Turn-On Response Time
Turn-Off Response Time
CDMA/FM Pin High Selects CDMA, Low Selects FM
PD1 and PD2 Pins Low Select IC ON, High Selects IC OFF
To 200 µA Supply Current
1.34
1.30
0.1
430
2.8
6.8
V
V
µA
ns
µs
µs
LOW DROPOUT REGULATOR
Input Range
Nominal Output
Voltage Drop
Reference Output
External PNP Pass Transistor, VCESAT = –0.4 V Max
hFE = 100/300 Min/Max
2.9 4.2
2.70
200
1.23
V
V
mV
V
POWER SUPPLY
Supply Range Using Internal LDO
Supply Range Bypassing Internal LDO
Supply Current
Standby Current
Supply Input at Pin LDOE
Supply Input at Pins DVCC, IFVCC, LDOC
VGAIN = 1.5 V
2.9–5.0
2.7–3.6
10
0.78
V
V
mA
µA
OPERATING TEMPERATURE
TMIN to TMAX
Specifications subject to change without notice.
–40 +85 °C
–2– REV. B


Part Number AD6121
Description CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator
Maker Analog Devices
Total Page 16 Pages
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