Datasheet Summary
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2.5 MSPS, 20-Bit Σ∆ ADC
Preliminary Technical Data
Features
High performance 20-bit Sigma-Delta ADC 118dB SNR at 78kHz output data rate 100dB SNR at 2.5MHz output data rate 2.5 MHz maximum fully filtered output word rate Programmable over-sampling rate (8x to 256x) Flexible parallel interface Fully differential modulator input On-chip differential amplifier for signal buffering Low pass FIR filter with default or user programmable coefficients Over-range alert bit Digital offset and gain correction registers Filter bypass modes Low power and power down modes Synchronization of multiple devices via SYNC pin
VIN- VIN+
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3...