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AD9212 - Serial LVDS A/D Converter

Description

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Features

  • 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) ENOB = 9.8 bits SFDR = 80 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-cha.

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Full PDF Text Transcription

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Data Sheet Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC AD9212 FEATURES 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) ENOB = 9.8 bits SFDR = 80 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.
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