AD9517-2 - 12-Output Clock Generator

Analog Devices

Datasheet Details

Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.05 GHz to 2.33 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 2 pairs of 1.6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay.

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Published: Jan 2, 2017 |