Datasheet4U Logo Datasheet4U.com

AD9652 - 3.3V / 1.8V Dual Analog-to-Digital Converter

General Description

The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS.

It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz).

Key Features

  • High dynamic range SNR = 75.0 dBFS at 70 MHz (AIN =.
  • 1 dBFS) SFDR = 87 dBc at 70 MHz (AIN =.
  • 1 dBFS) Noise spectral density (NSD) =.
  • 156.7 dBFS/Hz input noise at.
  • 1 dBFS at 70 MHz NSD =.
  • 157.6 dBFS/Hz for small signal at.
  • 7 dBFS at 70 MHz 90 dB channel isolation/crosstalk On-chip dithering (improves small signal linearity) Excellent IF sampling performance SNR = 73.7 dBFS at 170 MHz (AIN =.
  • 1 dBFS) SFDR = 85 dBc at 170 MHz (AIN =.
  • 1.

📥 Download Datasheet

Datasheet Details

Part number AD9652
Manufacturer Analog Devices
File Size 1.38 MB
Description 3.3V / 1.8V Dual Analog-to-Digital Converter
Datasheet download datasheet AD9652 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
AD9256 DIGITAL AMPLIFIER POWER STAGE Elite Semiconductor
AD9256H DIGITAL AMPLIFIER POWER STAGE Elite Semiconductor
AD92580 DIGITAL AMPLIFIER POWER STAGE Elite Semiconductor
AD92580C DIGITAL AMPLIFIER POWER STAGE Elite Semiconductor
AD9700 Video Dispaly D/A Converter ETC

Other Datasheets by Analog Devices

Part Number Description
AD9650 1.8 V Dual Analog-to-Digital Converter
AD9653 Serial LVDS 1.8V Analog-to-Digital Converter
AD9655 1.8V Analog-to-Digital Converter
AD9656 1.8 V Analog-to-Digital Converter
AD9600 1.8 V Dual Analog-to-Digital Converter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Data Sheet 16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC) AD9652 FEATURES High dynamic range SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS) SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS) Noise spectral density (NSD) = −156.7 dBFS/Hz input noise at −1 dBFS at 70 MHz NSD = −157.6 dBFS/Hz for small signal at −7 dBFS at 70 MHz 90 dB channel isolation/crosstalk On-chip dithering (improves small signal linearity) Excellent IF sampling performance SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS) SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS) Full power bandwidth of 465 MHz On-chip 3.3 V buffer Programmable input span of 2 V p-p to 2.5 V p-p (default) Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.