cmos 200 msps 14-bit quadrature digital upconverter.
200 MHz internal clock rate 14-bit data path Excellent dynamic performance:
80 dB SFDR @ 65 MHz (±100 kHz) AOUT 4× to 20× programmable reference clock multiplier Referenc.
HFC data, telephony, and video modems Wireless base station Agile, LO frequency synthesis Broadband communications
PARA.
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