ADCLK925 Datasheet | Analog Devices

.. Ultrafast Si Ge ECL Clock/Data Buffers ADCLK905/ADCLK907/ADCLK925 TYPICAL APPLICATION CIRCUITS VREF VT VCC Features 95 ps propagation delay 7.5 GHz toggle rate 60 ps typical output rise/fall 60 fs random jitter (RJ) On-chip terminations at both input pins Extended industrial temperature range: - 40°C to +125°C 2.5 V to 3.3 V power supply (VCC - VEE) 06318-001 APPLICATIONS Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer VREF 1 V T1 VCC D1 D1 VEE VEE D2 D2 VCC VREF 2 06318-002 GENERAL DESCRIPTION The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (Si Ge) bipolar process. The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply. The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ). The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs. The ECL output stages are designed to directly drive 800 m V each side into 50 Ω terminated to VCC - 2 V for a total differential output swing of 1.6 V. The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages. Q1 Q1 Q2 Q2 V T2 Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer VREF VT VCC Q1 Q1 D D Q2 06318-003 Q2 VEE Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog...