3.5 pF off source capacitance
Off drain capacitance
ADG5206: 64 pF
ADG5207: 33 pF
0.35 pC typical charge injection
±0.02 nA on channel leakage
Low on resistance: 155 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
VSS to VDD analog signal range
Human body model (HBM) ESD rating
ADG5206: 8 kV all pins
ADG5207: 8 kV I/O port to supplies
Automatic test equipment
The ADG5206 and ADG5207 are monolithic CMOS analog
multiplexers comprising 16 single channels and 8 differential
channels, respectively. The ADG5206 switches one of sixteen
inputs to a common output, as determined by the 4-bit binary
address lines, A0, A1, A2, and A3. The ADG5207 switches one
of eight differential inputs to a common differential output, as
determined by the 3-bit binary address lines, A0, A1, and A2.
An EN input on both devices enables or disables the device. When
EN is low, the device is disabled and all channels switch off. The
ultralow capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make these
devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
High Voltage, Latch-Up Proof,
FUNCTIONAL BLOCK DIAGRAMS
A0 A1 A2 A3 EN
A0 A1 A2 EN
The ADG5206/ADG5207 do not have VL pins; instead, an on-chip
voltage generator generates the logic power supply internally.
1. Trench Isolation Guards Against Latch-Up. A dielectric trench
separates the P and N channel transistors to prevent latch-up
even under severe overvoltage conditions.
2. Optimal switch design for low charge injection, low switch
capacitance, and low leakage currents.
3. The ADG5206 achieves 8 kV HBM ESD specification on
all external pins, while the ADG5207 achieves 8 kV on the
I/O port to supply pins, 2 kV on the I/O port to I/O port
pins, and 8 kV on all other pins.
4. Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5206/ADG5207 can be operated
from dual supplies of up to ±22 V.
5. Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5206/ADG5207 can be
operated from a single rail power supply of up to 40 V.
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